Loop filters are commonly utilized as functional blocks in PLLs, among other types of circuits. FIG. 1 illustrates a conventional PLL 100 comprised of three functional blocks, namely, a phase detector 102, a loop filter 104, and a voltage-controlled oscillator (VCO) 106. These three blocks 102, 104, 106 are interconnected in a feedback arrangement as shown. Such PLLs may be implemented in ICs used in a wide variety of electronic systems and applications, including, for example, communication systems. The basic theory and principle of operation of PLLs are well known, as described, for example, in Alan B. Grebene, “Bipolar and MOS Analog Integrated Circuit Design,” pp. 627–678 (John Wiley & Sons 1984), which is incorporated herein by reference. Consequently, the theory and principle of operation of PLLs in general will not be presented in detail herein.
The loop filter has a strong influence on the overall performance characteristics of the PLL. For example, when the PLL is in a locked state, a transfer function of the loop filter, along with a loop gain, determine both the transient response and the frequency response characteristics of the PLL. When the PLL is not locked, the loop filter has a dominant effect in controlling the ability of the PLL to lock to an input signal. The loop filter may further significantly affect, for example, PLL bandwidth, reference jitter rejection and/or power supply jitter rejection. In a radio frequency (RF) application, for example, the loop filter may additionally function to filter out difference frequency components associated with undesired signals which are far removed from a free-running frequency of the VCO. In this manner, the loop filter enhances the interference rejection characteristics of the PLL. The PLL essentially captures only those signals that are close to the free-running frequency of the VCO, such that a difference frequency Δf falls approximately within the bandwidth of the loop filter, where Δf may be defined as a magnitude of the difference between the free-running frequency of the VCO and the frequency of an input signal VS(t) applied to the PLL.
Since the loop filter 104 is typically configured as a low-pass filter having a bandwidth of about one megahertz (MHz) or so, it is necessary for the loop filter to employ relatively large value capacitors. The large value capacitors are often implemented as metal-oxide semiconductor field-effect transistors (MOSFETs). The MOSFET gate oxide generally offers the thinnest oxide, and thus the highest capacitance density, available for a given IC fabrication process. For example, a conventional 0.13 micron complementary metal-oxide-semiconductor (CMOS) IC fabrication process provides MOSFET devices having a gate oxide thickness of about 17 angstroms.
As IC fabrication process dimensions are scaled down, gate oxide thickness generally shrinks accordingly, which typically causes an increase in tunneling through the thin gate oxide. As the gate oxide thickness falls below about 20 angstroms, this gate oxide tunneling often produces a significant leakage current which can overwhelm the PLL, causing the PLL to have difficulty achieving lock. Even when lock is established in the PLL, the leakage current typically appears as a static phase offset between the input signal VS(t) and a VCO output signal VO(t) fed back to the phase detector. This static phase offset directly translates to jitter on the output signal of the PLL.
Previous attempts to reduce the leakage current attributed to the thin-oxide MOSFET capacitors employed in the loop filter of a PLL have involved a compensation scheme which accounts for an average leakage current in the loop filter. This approach, however, requires the inclusion of additional compensation circuitry in the PLL which is often complex and is thus undesirable. Furthermore, the compensation circuitry may suffer from mismatch and must therefore be calibrated to a reference device. Since the compensation circuitry generally only adjusts for average leakage current in the loop filter, any uncompensated leakage current will appear as phase offset and jitter in the output signal generated by the PLL.
Patent Publication No. US 2003/0124810 A1 to Tam et al. (hereinafter “Tam”) addresses a solution for reducing leakage current in a single-loop PLL resulting from the thin-oxide MOSFET capacitor in the loop filter by replacing the thin-oxide capacitor with a thick-oxide N-type MOSFET (NMOS) device. In the Tam PLL configuration, the voltage for controlling the VCO is placed directly across the thick-oxide NMOS device. This control voltage can vary widely and, in some instances, the thick-oxide NMOS device may not be able to turn on depending on the control voltage level.
To solve this problem, Tam discloses a methodology for lowering the threshold voltage of the thick-oxide NMOS device by doping the gate terminal of the device with a P-type dopant. However, since the capacitance value of the thick-oxide NMOS device is significantly voltage dependent, the capacitance of the device will change with variations in the control voltage. Thus, not only does the Tam methodology require additional IC fabrication steps to modify the conventional thick-oxide device, thereby increasing the manufacturing cost of the PLL, but the transfer characteristics of the loop filter will vary widely as a function of the VCO control voltage, which is undesirable.
There exists a need, therefore, for an improved loop filter for use in a PLL, that does not suffer from one or more of the problems exhibited by conventional PLL arrangements. Moreover, it would be desirable if the improved loop filter were compatible with existing IC fabrication process technologies.